1. Field of the Invention
This invention relates to a semiconductor device advantageous for miniaturization.
2. Description of the Prior Art
There occurs the problem that, with development of miniaturization of the MISFET (Metal Insulation Silicon Field Effect Transistor), punch-through is apt to take place between the drain and source by the short-channel effect. With a view to solving this problem, a LDD (lightly doped drain) structure has been conventionally devised. Namely, this LDD structure is a structure having a lightly doped drain-source. When attention is drawn to, e.g., an n-channel MOSFET, the field oxide film sides of the drain region and the source region are caused to be an n.sup.+ layer. The channel formation layer sides thereof are caused to be an n.sup.- layer, to set the impurity concentration at the channel side end portions of the drain and the source to a relatively lower value and thereby relax the drain electric field. This improves the withstand voltage, and prevents punch-through(penetration) between the drain and the source by the short-channel effect.
FIGS. 1A-1D show particularly a method of forming diffused layers serving as source and drain regions of in a typical manufacturing process for a MOSFET having such a LDD structure and its LDD elemental device structure.
In these figures, ion implantation for forming wells is first implemented into a silicon substrate 701 thereafter to carry out extending diffusion of the implanted impurity, to thereby form a well to subsequently carry out an ion implantation for prevention of a parasitic channel. Thereafter, selective oxidation is implemented onto the substrate 701 surface to form field oxide film 702 to carry out isolation of the elemental device region (hereinafter simply referred to as the device region) from each other. Then, a gate electrode material oxide film is formed by thermal oxidation on the entire surface of the region surrounded by the oxide film 702 on the substrate 701 to subsequently form a gate electrode material polycrystalline silicon (hereinafter polysilicon) film on the entire surface of the oxide film by using the LPCVD process so that its thickness reaches 2,000 angstroms. Thereafter, a mask of photoresist is formed on the polysilicon film serving as a gate electrode material by the optical lithography to implement patterning to the gate electrode material oxide film and the gate electrode material polysilicon film by using the RIE process thus to form a gate electrode comprised of a gate oxide film 703 and a polysilicon film 704 (FIG. 1A).
In the case where the MOSFET to be manufactured is a p-channel MOSFET, implantation of ions 705 of impurity BF.sub.2.sup.+ is then carried out using a low dose (about 1.times.10.sup.13 cm.sup.-2) and an acceleration voltage of about 30 KeV (FIG. 1B). In the figure, reference numeral 706 represents a low concentration ion implanted region which is to serve as a source formed by that ion implantation, and reference numeral 707 represents a low concentration ion implanted region which is to serve as a drain formed by that ion implantation.
Thereafter, a silicon oxide film is deposited on the entire surface of substrate 701 by the LPCVD process, so that its thickness reaches about 1000 angstroms to subsequently carry out the RIE process, thereby allowing oxide film portions 708, 709 formed in a side wall to be left on the side surfaces of the gate electrode. Further, the implantation of ions 705 of impurity BF.sub.2.sup.+ is, in turn, carried out ordinarily under the condition of a higher dose more than 1.times.10.sup.15 cm.sup.-2 and an acceleration voltage of about 30 KeV (FIG. 1C). Thus, a high concentration ion implanted region 710 is formed at the portion which is to serve as the source on the substrate 701, and a high concentration ion implanted region 711 is formed at the portion which is to serve as the drain on the substrate 701.
Then, the RTA (Rapid Thermal Annealing) process is carried out for 20 seconds at 1000.degree. C. Then, after the activation of ion implanted impurity has been conducted, metal silicide films 714, 715 are formed on the surface portions of the respective ion implanted regions 710, 711 by the salicide (Self Align Silicide) process to thereby carry out activation of impurity to form the source region comprised of a high concentration diffused layer 716 and a low concentration diffused layer 717 and the drain region comprised of a high concentration diffused layer 718 and a low concentration diffused layer 719. Thus, LDD structures (low concentration diffused layers 717, 719) shallow in depth which have a low carrier concentration in correspondence with a carrier concentration of the substrate 701 are formed on the both sides of the channel formation region below the gate oxide film 703 (FIG. 1D).
Meanwhile, although such LDD structure has an advantage of suppression of the short-channel effect as previously described, it has the problem that since the channel side portions of the drain and source have a low concentration, the resistance between the source and the drain increases by lowering of the concentration, resulting in a lowered current drivability. For this reason, in the case where the short-channel effect is not so great a problem in relation to the power supply voltage specification, there were instances where such a LDD structure is not employed.
However, it is considered that the action of suppression of the short-channel effect by the LDD structure is very useful for miniaturization of a MOSFET. In view of this, the present inventors conducted a simulation to study an optimum mode (structure, impurity profile, etc.) of this LDD structure. As a result, it is found that from the points of view of both suppression of the short-channel effect and assuring drivability, the construction, in which a shallow diffused layer having high concentration which cannot be realized by optimizing the conventional method and a diffused layer required to have a certain depth when the salicide process, is taken into consideration.